Conventional general purpose three-dimensional (3D) electromagnetic modeling (EM) simulators that incorporate volume discretization techniques, such as the finite elements method (FEM) or the finite-difference time domain (FDTD) method, are suffering from the excessive computer processing and storage capacity that is needed for adequately modeling conductor structures coated with thin layers of dielectric material, referred to as dielectric coatings. The number of mesh elements to be included in the modeling process is prohibitively large due to large aspect ratio differences of thin dielectric coating layers in combination with large 3D conducting objects. Therefore, general purpose 3D EM simulators can only be applied for structures with limited geometrical complexity.
Similarly, 3D EM simulators that use surface discretization techniques, such as the boundary element method (BEM), have essentially the same problem. Such 3D EM simulators introduce equivalent electric and magnetic surface currents at boundaries of the dielectric coating and conductive objects. Incorporating the effects of the dielectric coating dramatically increases the size of the discretized problem to be solved, again exceeding processing and storage capacity.
One class of 3D EM simulators, referred to as 3D planar EM simulators, takes advantage of the Green's function technology to incorporate the effects of a dielectric layer stack (also known as the substrate) in the simulation without additional discretization cost for the dielectric layers. The 3D planar simulators deploy integral equations and conductor surface meshing techniques to model the electromagnetic effects of 3D finite conductors embedded in the dielectric layers. However, the Green's function technology only supports dielectric layers that are planar and extend to infinity, and therefore cannot handle finite 3D dielectric layers and coatings in the solution process.
Other conventional 3D EM simulators provide application focused solutions. For example, one conventional through-silicon via (TSV) modeling approach is based on integral equations derived from Maxwell's equations in combination with circuit theory to combine a series RL-model for the conductor current and a parallel GC-model for the substrate current with an excess capacitance for the polarization currents in the TSV liner dielectric in an equivalent RL-GC network for the TSV structure. The TSV liner dielectric can be viewed as a coating of the TSV conductor. An example of the TSV modeling approach is described by Swaminathan et al., “3D Modeling of Through-Silicon Vias (TSVs), a Key Enabling Technology for 3D Integration,” Interconnect and Packaging Center, Georgia Institute of Technology (Mar. 27, 2009), and K. J. Han et al., “Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions,” IEEE Trans. Advanced Packaging, vol. 33, no. 4, pp. 804-817, November 2010. The TSV modeling approach deploys global cylindrical basis functions instead of meshing to provide rapid modeling (fewer unknowns) for the TSV structures. The use of global basis functions reduces computational cost and model complexity and enables the simulation of large arrays of TSVs. However, the TSV modeling approach embeds the geometry specifics of TSV structures and therefore lacks flexibility to be applicable to more general structures. Technologies based on meshing are more flexible in dealing with general geometries.
Further, conventional solutions do not account for the voltage dependent metal-oxide-semiconductor (MOS) effect that takes place at the silicon contact surface, where the metal is the TSV conductor, the oxide is the dielectric coating, and the semiconductor is silicon. The MOS structure introduces an effect of accumulation, depletion and inversion of the major carriers in the silicon that depend on substrate doping and TSV bulk voltage. The voltage dependent depletion layer in the silicon bulk changes the TSV isolation. This effect is also included in the modeling process.